1. Field of the Invention
The present invention relates generally to integrated circuit electronic devices on a single chip and more particularly to programmable sequencing elements.
2. Description of the Related Art
Programmable sequencing elements comprise a family of devices which share a similar basic logic architecture. The block diagram of FIG. 1 illustrates this basic architecture. The architecture includes an AND-array which receives input signals, performs AND logic functions using the input signals and provides AND function signals as outputs. It also includes an OR-array, which receives the AND function signals from the AND-array, performs OR logic functions using the AND function signals and provides AND-OR signals as outputs. This basic architecture is useful in implementing Boolean sum-of-products type algebra.
The programmable sequencing elements include programmable read only memories (PROMs), programmable array logic devices and programmable logic arrays (PLAs). PROM architecture includes a fixed AND-array and a programmable OR-array. Programmable array logic devices include a fixed OR-array and a programmable AND-array. PLAs include a programmable AND-array and a programmable OR-array.
A typical PROM comprising n input terminals for receiving n binary input signals, usually includes 2.sup.n AND gates in its AND-array. A respective AND gate ordinarily corresponds to each possible combination of binary signals provided to the n input terminals. Thus, input signals provided to a PROM are fully decoded in that each possible combination of input signals provided to the PROM corresponds to a particular AND gate of the AND-array. The OR-array, therefore, can be programmed to store a distinct combination of binary data for every possible combination of binary input signals.
Programmable array logic devices, unlike PROMs, are not restricted by the requirement that there be 2.sup.n AND gates for n input terminals. A typical earlier programmable array logic device is disclosed in U.S. Pat. No. 4,124,899 issued to Birkner et al on Nov. 7, 1978. A programmable array logic device, therefore, ordinarily can include more input signal terminals than it has AND gates. Unfortunately, however, some possible combinations of binary input signals provided to the input terminals of a typical programmable array logic device are unaccounted for in that they do not correspond to particular output signals provided by the device.
PLAs, while featuring many of the advantages of both PROMs and programmable array logic devices, suffer from an important disadvantage. Typical PLAs are described in Handbook of Semiconductor and Bubble Memories by Walter A. Triebel and Alfred E. Chu copyright 1983 by Prentice-Hall, Inc., pages 220-257. Typically they are much slower than the other types of programmable sequencing elements, and therefore, ordinarily are not suitable for high-speed environments.
One important performance goal for programmable sequencing elements has been flexibility of operation. For example, one prior U.S. patent application owned by the assignee in common with the present application, entitled APPARATUS FOR PRODUCING ANY ONE OF A PLURALITY OF SIGNALS AT A SINGLE OUTPUT, Ser. No. 433,253, now U.S. Pat. No. 4,717,912 filing date Oct. 7, 1982 addresses one way in which the configuration of input/output ports may be made more flexible. Moreover, another prior U.S. patent application entitled DYNAMICALLY CONTROLLABLE OUTPUT LOGIC CIRCUIT, Ser. No. 656,109, now abandoned, filing date Sep. 20, 1984 addresses an output logic circuit for controlling the configuration of an output which allows for dynamic control of the configuration and increases the flexibility of design for the user of the invention.
While these earlier programmable sequencing elements generally have been successful, there have been shortcomings with their use. For example, since PROMs usually decoded substantially every possible binary input signal combination provided to their input terminals, each respective binary input signal combination corresponded to a respective AND gate coupled to the PROM OR-array. As a result, only one test condition ordinarily could be tested per cycle of the PROM, and the state machine, therefore, could not perform multiple branching. That is, the state machine could not transition from one state to any one of two or more other states based upon multiple test conditions. Thus, such earlier state machines often required a larger number of cycles than was desirable in order to achieve a transition between states involving multiple test conditions.
Therefore, although earlier PROMs offered some advantage over typical programmable array logic devices by fully decoding all possible binary input signal combinations and over prior PLAs due to superior speed, such earlier PROMs suffered shortcomings due to their fixed input and output terminal structures and due to the fixed nature of the output signals provided by those terminals. Furthermore, prior PROMs often were inefficient in the implementation of flexible state machines.
Thus, there exists a need for an apparatus in which a PROM can implement a state machine capable of testing multiple test conditions during each PROM cycle, and which is capable of flexible multiple branching from one state to any one of at least two other states. The present invention meets this need.